Image and Signal Processing Research Group

Image and Signal Processing using Field Programmable Gate Arrays

With the need for increased speed and integration, many real-time image and signal processing algorithms must be implemented in hardware. In the past this was through the design of dedicated processors. However, field programmable gate arrays (FPGAs) have matured to the stage where they now offer a practical and relatively inexpensive alternative to dedicated hardware. This project investigates aspects of mapping the algorithms for image processing and signal processing onto FPGAs.

 

Participating Staff

• Donald Bailey (Project Leader)
  

Students

• Aaron Bishell (MSc: 2007-2008) "Designing Application Specific Processors for Image Processing"
• Andreas Buhler (ME: 2006-2007) "GateOS: A minimalist Windowing Environment and Operating System for FPGAs"
• Cameron Baker (FYP: 2005) "Interfacing FPGA to External Devices"
  
• Chris Johnston (PhD: 2004-     )
• Kim Gribbon (PhD: 2003-      )
• Chris Johnston (FYP: 2003) "A Real-Rime FPGA Implementation of Barrel Distortion Correction Algorithm"
  
• David Johnson (FYP: 2002) "Hardware Implementation of Digital Signal Processing Algorithms"
  

Publications

• N. Ma, D. Bailey, and C. Johnston, "Optimised single pass connected components analysis", in International Conference on Field Programmable Technology, Taiwan (8-10 December, 2008).
• D. Bailey and C.-S. Bouganis, "Reconfigurable foveated active vision system", in International Conference on Sensing Technology, Taiwan (30 November - 3 December, 2008).
• D.G. Bailey, C.T. Johnston, and N. Ma, "Connected components analysis of streamed images", in International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 679-682 (8-10 September, 2008).
• C.T. Johnston, P. Lyons, and D.G. Bailey, "A Visual Notation for Processor and Resource Scheduling", in IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), Hong Kong, pp 296-301 (23-25 January, 2008).
• C.T. Johnston and D.G. Bailey, "FPGA implementation of a Single Pass Connected Components Algorithm", in IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), Hong Kong, pp 228-231 (23-25 January, 2008).
• D.G. Bailey and C.T. Johnston, "Single Pass Connected Components Analysis", in Image and Vision Computing New Zealand, Hamilton, New Zealand, pp 282-287 (5-7 December, 2007).
• K.T. Gribbon, D.G. Bailey, and A. Bainbridge-Smith, "Development Issues in Using FPGAs for Image Processing", in Image and Vision Computing New Zealand, Hamilton, New Zealand, pp 217-222 (5-7 December, 2007).
• A.D. Bishell, D.G. Bailey, and P. Lyons, "Designing Custom Processors on FPGAs for Specific Applications", in Electronics New Zealand Conference, Wellington, NZ, pp 7-12 (12-13 November, 2007).
• D.G. Bailey, "Space Efficient Division on FPGAs", in Electronics New Zealand Conference (EnzCon'06), Christchurch, NZ, pp 206-211 (13-14 November, 2006).
• C.T. Johnston, D.G. Bailey, and P. Lyons, "A Visual Environment for Real Time Image Processing in Hardware (VERTIPH)", EURASIP Journal on Embedded Systems, 2006:(Article ID 72962) 8 pages (2006)
• C.T. Johnston, D.G. Bailey, and P. Lyons, "Towards a Visual Notation for Pipelining in a Visual Programming Language for Programming FPGAs", in 7th International Conference of the NZ chapter of the ACM's Special Interest Group on Human-Computer Interaction (CHINZ 2006), Christchurch, NZ, ACM International Conference Proceeding Series, 158: 1-9 (July 6-7, 2006).
  
• K.T. Gribbon, C.T. Johnston, D.G. Bailey, "Formalizing Design Patterns for Image Processing Algorithm Development on FPGAs", Proceedings of the third IEEE International Workshop on Electronic Design, Test, and Applications (Delta 2006), Kuala Lumpur, Malaysia, pp 47-53 (17-19 January, 2006)
• Donald Bailey, Kim Gribbon, Chris Johnston, "GATOS: A Windowing Operating System for FPGAs", Proceedings of the third IEEE International Workshop on Electronic Design, Test, and Applications (Delta 2006), Kuala Lumpur, Malaysia, pp 405-409, (17-19 January, 2006)
• C.P. Baker, D.G. Bailey, "Interfacing hardware to FPGAs", Projects Journal, 14, pp 1-5 (2005)
• C.T. Johnston, D.G. Bailey, K.T. Gribbon, "Optimisation of a colour segmentation and tracking for real-time FPGA implementation", Image and Vision Computing New Zealand, Dunedin, pp 422-427 (28-29 November, 2005)
• Christopher T. Johnston, Kim T. Gribbon, Donald G. Bailey, "FPGA Based Remote Object Tracking for Real-time Control", International Conference on Sensing Technology, Palmerston North, pp 66-71 (21-23 November 2005)
• K.T. Gribbon, C.T. Johnston, D.G. Bailey, "Formalizing Design Patterns for Image Processing Algorithm Development on FPGAs", IEEE Tencon'05, Melbourne, Australia, (21-24 November 2005)
• K. Gribbon, D.G.Bailey, C.T. Johnston, "Colour edge enhancement", Proceedings Image and Vision Computing New Zealand 2004, Akaroa, New Zealand, pp 291-296 (November 2004)
• C.T. Johnston, D.G.Bailey, P. Lyons, K.T. Gribbon, "Formalisation of a Visual Environment for Real Time Image Processing in Hardware (VERTIPH)", Proceedings Image and Vision Computing New Zealand 2004, Akaroa, New Zealand, pp 297-302 (November 2004)
• C.T. Johnston, K.T. Gribbon, D.G. Bailey, “Implementing Image Processing Algorithms on FPGAs”, Proceedings of the Eleventh Electronics New Zealand Conference, ENZCon’04, Palmerston North, New Zealand, pp 118-123 (November 2004)
• K.T. Gribbon, D.G. Bailey, “A Novel Approach to Real Time Bilinear Interpolation”, Proceedings of the IEEE International Workshop on Electronic Design, Test, and Applications, Perth, Australia, pp 126-131 (January 2004).
• C.T. Johnston, D.G. Bailey, “A Real-time FPGA Implementation of a Barrel Distortion Correction Algorithm”, Projects Journal, 12: 91-96 (2003)
• K.T. Gribbon, C.T. Johnston, D.G. Bailey, “A Real-time FPGA Implementation of a Barrel Distortion Correction Algorithm with Bilinear Interpolation”, Proceedings of Image and Vision Computing New Zealand, Palmerston North, New Zealand, pp 408-413 (November 2003).
• D.J. Johnson, D.G. Bailey, S.N. Demidenko, “Hardware Implementation of Digital Signal Processing Algorithms”, Projects Journal, 11: 104-109 (2002).
• D Johnson, K. Gribbon, D Bailey, and S. Demidenko, "Implementing Signal Processing Algorithms in FPGAs: Digital Spectral Warping", in Ninth Electronics New Zealand Conference (ENZCon'02), Dunedin, New Zealand, 72-77 (14-15 November, 2002).